In applications where access time is not critical, dynamic random access memory devices (DRAMs) have several advantages over other types of memories, in particular, static random access memories (SRAMs). In comparison to SRAMs, DRAMs are less expensive, consume substantially less power, and provide more bits in the same chip space (i.e. have a higher cell density). Hence, DRAMs are normally used to construct those memory subsystems, such as system memories and display frame buffers, where power conservation and high cell density are more critical than speed. In most computing systems, it is these subsystems which dominate the system architecture, and thus, DRAMs are the prevalent type of memory device on the market.
The cells of the typical DRAM array are arranged in rows and columns. A row is selected for access by activating a corresponding conductive wordline. Data accesses (reads and writes) are made to the cells of the selected row through conductive bitlines associated with each of the corresponding columns. Conventionally, each bitline is formed by a pair of half-bitlines. The cells coupled to one half-bitline form part of one set of rows, for example the even rows, and are therefore controlled by the corresponding set of even wordlines. Similarly, the cells coupled to the other half-bitline form part of a second set of rows, for example the odd rows, and are controlled by the corresponding set of even wordlines. A differential sense amplifier is provided to sense the voltage difference between each half-bitlines pairs during an access.
Wordline activation is by row address, as decoded by a row decoder. Typically, all cells of a selected row are activated and their data sensed and latched by the sense amplifiers. A column decoder coupled to the sense amplifiers selects one or more of the physical columns for access in response to a column address. For example, in a "by 8" device, eight physical columns are accessed per column address.
The vast majority of DRAMs require two operational. periods per row access (precharge and active), as timed by a row address strobe (/RAS) and a column address strobe (/CAS). These two periods together constitute one cycle. When /RAS is in a logic high state, the DRAM device is in a precharge cycle, during which the nodes of various dynamic circuits, such as those used in the column and row decoders, are pulled to a predetermined voltage. Most importantly, during the precharge cycle the bitlines of the cell array are voltage equalized. Then, when /RAS transitions to a logic low, the device enters the active cycle. In Synchronous DRAM's, where a master clock controls the operation, /RAS and /CAS are timed off that particular master clock.
Typically, during the active cycle, the row address bits are presented to the address pins and latched into the DRAM device with the falling edge of /RAS. After a very small delay for set up, the column address bits are presented at the address pins and latched-in with the falling edge of /CAS. A short time thereafter the addressed cells (location) can be accessed. During page mode, additional column addresses are input with additional falling edges of /CAS (/CAS cycling) to access a series of "pages" along the selected row. At the end of the active cycle, /RAS returns to a logic high state and the device re-enters precharge (in any event, when a change in row is required, a complete new /RAS cycle, including a new precharge cycle and a new active cycle must be initiated.)
During a voltage-high precharge, all of the half-bitlines in the array are precharged to a predetermined voltage, for example 3.3 volts for a 3.3 V Vcc device, and then allowed to float (in some devices, precharge is to substantially zero volts but for purpose of the present discussion, precharge towards Vcc is assumed). Currently, the typical precharge cycle is between 50-60 nsec in length (the typical active row-reader or row-write cycle also known as random access cycle is also approximately 50-60 nsec long). While the nodes of most of the dynamic circuitry, such as that used in the row and column decoders, can be charged or discharged within 10 nsecs, the full 50 to 60 nsecs is required to precharge and equalize the bitlines of the cell array. A page cycle, or a burst cycle in a Synchronous DRAM could be shorter.
During the active cycle, the wordline selected in response to the received row address is activated and all the cells along the corresponding row are turned on. In this disclosure, all logic is positive--namely Logic 0 is V.sub.SS and Logic 1 is V.sub.CC. If the storage capacitor of a given activated cell is at ground potential(a logic 0), the corresponding half-bitline is pulled down slightly relative to the complementary half-bitline (the voltage on which is set by a reference or "dummy" cell). If the storage capacitor of a given active cell is at a higher voltage charge (a logic 1) the corresponding half-bitline is pulled up slightly (or maintained at V.sub.CC) relative to its complementary half-bitline. During a read or refresh, the sense amplifiers differentially detect the voltage different between each half-bitline pair and latch one half-bitline of the pair to a full logic high and the other to a full logic low, depending on the direction of the swing. During a write of a logic 0, the sense amplifiers pull down the half-bitline which is to carry the logic zero and latch-high the other half-bitline. A write of a logic 1 is similar.
The voltage swings caused by the cell storage capacitors on the bitlines are extremely small. The typical storage cell capacitor has a capacitance of approximately 25-35 fF (femtofarads) while the half-bitline it couples with has a capacitance of approximately 300-500 fF. Therefore, to avoid incorrect sensing of the stored logic state, the precharge voltage on each bitline pair must be equalized during precharge as closely as possible. Notwithstanding, some voltage imbalance will always exist, often on the order of 2 to 3 millivolts. For example, constraints on the chip fabrication processes result in differences in the resistance and capacitance between the half-bitlines in each half-bitline pair. Similarly, the widths and lengths of the channels, and thus threshold voltages and gains, will vary between the (cross coupled) transistors in the sense amplifiers.
Additional problems must be accounted for during sensing. For example, it would be desirable to turn-on the sense amplifiers very quickly (e.g. on the order of 5 nanoseconds) to provide a short access time. However, if the "bottom" transistor controlling current flow through the sense amplifier differential transistor pair is turned on rapidly, capacitive coupling effects can cause unwanted voltages to couple to half-bitlines and cause mis-sensing.
Thus, the need has arisen for precision sense amplifier circuitry and methods and systems using the same. Among other things, such circuitry and methods should allow for fast, accurate sensing. In particular, problems associated with the differential sensing of small voltages should be accounted for while minimizing the coupling of noise voltage from the bottom capacitor. These circuits and methods should preferably be applicable to DRAMs, but should also be adaptable for use in other types of memories, such as SRAMs.